Rahul Shukla
@Rahul63076VLSI Design & Verification Enthusiast Skilled in Verilog, SystemVerilog, UVM verification & RTL design. || BTech || Electrical Engineering.
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Prajwal Malabagi
@Prajwal03Malabagi
Arman Hussain
@ArmanHussain786
Aman Hussain
@Amanhussain786
Utkarsh Pandey
@utkarsh63069
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The APB–SPI Master interface acts as a bridge between an APB-based processor and SPI peripherals like sensors or memory. It enables the processor to control SPI communication through simple register read/write operations
This project verifies an APB-based SPI core using a SystemVerilog UVM testbench. It ensures protocol compliance, configurability, and robustness across conditions. Key features validated include CPOL, CPHA, LSB/MSB selection, baud rate control, and low-power modes through comprehensive test scenarios and coverage analysis.
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